1. Field of the Invention
The present invention relates to a method and circuit for transferring data, and more especially, to a method and circuit for transferring data stream across multiple clock domains.
2. Background of the Related Art
It's quite common to transfer data stream in multiple clock domains in the electronic circuit. For example, referring to FIG. 1A, it depicts a circuit for transferring data in three clock domains. The data stream data_0 10 in domain D 14 is first sampled by sampling pulse clk1 17 to become a data stream data_1 11 in domain D+1 15; thereafter, the data stream data 111 is sampled by sampling pulse clk2 18 to become the data stream data_2 12 in domain D+2 16, and then the data stream data_2 12 is sampled by sampling pulse clk3 19 to become the data stream data_3.
Moreover, even though the frequency for all sampling clocks are the same, the skew and jitter may still happen around the sampling edges of different clocks (as shown in FIG. 1B, there is skew or jitter happened on the rising or falling edge of sampling pulse clk2 18, even the frequency of sampling pulse clk1 17 is equal to that of sampling pulse clk2 18) and such skew or jitter causes the phase difference and sampling ambiguity.
However, since the frequencies of sampling pulse clk1 17, clk2 18, and clk3 19 may be different, that makes the sampling ambiguity more serious in sampling processes. For example, as shown in FIG. 2, a first data stream comprises several frames (K−1, K, K+1), and each frame comprises 3 parallel bits, bit0, bit1 and bit2. The first data stream may be originally sampled by a sampling pulse clk1 and then sampled by faster sampling pulses clk2 to become a second data stream in a series format to be transmitted through a high speed series transmission line (ex, low voltage differential signaling, LVDS). The traditional solution to reduce the sampling ambiguity in this situation is using three different clocks sel_0, sel_1 and sel_2 to respectively sample the data 0, data 1, and data 2 to produce a series of bits containing bit0, bit1 and bit2 in the frame K. Besides, it may happen that, due to the skew or jitter, the clock sel_0 samples data0 at the edge of sampling pulse clk1, and that still causes sampling ambiguity.